1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device implementing in-plane switching (IPS) where an electric field to be applied to liquid crystal is generated in a plane parallel to a substrate.
2. Discussion of the Related Art
A typical liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientational order in alignment resulting from their thin and long shapes. The alignment of the liquid crystal molecules can be controlled by supplying an electric field to the liquid crystal molecules. In other words, as the alignment direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light is refracted to the orientation of the liquid crystal molecules due to the optical anisotropy of the aligned liquid crystal molecules, image data is displayed.
Liquid crystal is classified into positive liquid crystal and negative liquid crystal, depending on the electrical properties of the liquid crystal. The positive liquid crystal has a positive dielectric anisotropy such that long axes of liquid crystal molecules are aligned parallel to an electric field. Whereas, the negative liquid crystal has a negative dielectric anisotropy such that long axes of liquid crystal molecules are aligned perpendicular to an electric field.
By now, active matrix LCDs, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are widely used because of their high resolution and superiority in displaying moving video data.
FIG. 1 is a cross-sectional view illustrating a typical twisted nematic (TN) LCD panel. As shown in FIG. 1, the TN LCD panel has lower and upper substrates 2 and 4 and an interposed liquid crystal layer 10. The lower substrate 2 includes a first transparent substrate 1a and a thin film transistor (“TFT”) “S”. The TFT “S” is used as a switching element to change orientation of the liquid crystal molecules. The lower substrate 2 further includes a pixel electrode 15 that applies an electric field to the liquid crystal layer 10 in accordance with signals applied by the TFT “S”. The upper substrate 4 has a second transparent substrate 1b, a color filter 8 on the second transparent substrate 1b, and a common electrode 14 on the color filter 8. The color filter 8 implements color for the LCD panel. The common electrode 14 serves as another electrode for applying a voltage to the liquid crystal layer 10. The pixel electrode 15 is arranged over a pixel region “P,” i.e., a display area. A transparent conductive material like indium tin oxide (ITO) having superior light transmittance is used for the pixel electrode 15. Further, to prevent leakage of the liquid crystal layer 10 between the lower and upper substrates 2 and 4, those substrates are sealed by a sealant 6.
As described above, because the pixel and common electrodes 15 and 14 of the conventional TN LCD panel are positioned on the lower and upper substrates 2 and 4, respectively, the electric field induced therebetween is perpendicular to the lower and upper substrates 2 and 4. The above-mentioned liquid crystal display device has advantages of high transmittance and aperture ratio, and further, since the common electrode on the upper substrate serves as an electrical ground, the liquid crystal is protected from a static electricity.
However, the above-mentioned operation mode of the TN LCD panel has a disadvantage of a narrow viewing angle. To overcome the above-mentioned problem, an in-plane switching (IPS) LCD panel was developed. The IPS LCD panel implements a parallel electric field that is parallel to the substrates, which is different from the TN or STN (super twisted nematic) LCD panel. A detailed explanation about operation modes of a typical IPS LCD panel will be provided with reference to FIGS. 2, 3A, 3B, 4A and 4B.
As shown in FIG. 2, first and second substrates 1a and 1b are spaced apart from each other, and a liquid crystal “LC” is interposed therebetween. The first and second substrates 1a and 1b are called an array substrate and a color filter substrate, respectively. Pixel and common electrodes 15 and 14 are disposed on the first substrate 1a. The pixel and common electrodes 15 and 14 are parallel with and spaced apart from each other. On a surface of the second substrate 1b, a color filter 25 is disposed opposing the first substrate 1a. The pixel and common electrodes 15 and 14 apply an electric field “E” to the liquid crystal “LC”, then it is aligned parallel to the electric field “E”.
FIGS. 3A and 3B conceptually illustrate “off state” operation modes for a typical IPS LCD device. In an off state, the long axes of the LC molecules “LC” maintain a definite angle with respect to a line that is perpendicular to the pixel and common electrodes 15 and 14. The pixel and common electrode 15 and 14 are parallel with each other. Herein, the angle difference is 45 degrees, for example.
FIGS. 4A and 4B conceptually illustrate “on state” operation modes for the typical IPS LCD device. In an on state, an in-plane electric field “E”, which is parallel with the surface of the first substrate 1a, is generated between the pixel and common electrodes 15 and 14. The reason is that the pixel electrode 15 and common electrode 14 are formed together on the first substrate 1a. Then, the LC molecules “LC” are twisted such that the long axes thereof coincide with the electric field direction. Thereby, the LC molecules “LC” are aligned such that the long axes thereof are perpendicular to the pixel and common electrodes 15 and 14.
By the above-mentioned operation modes and with additional parts such as polarizers and alignment layers, the IPS LCD device displays images. The IPS LCD device has wide viewing angle and low color dispersion. Specifically, the viewing angle of the IPS LCD device is about 70 degrees in direction of up, down, right, and left. In addition, the fabricating processes of this IPS LCD device are simpler than other various LCD devices. However, because the pixel and common electrodes are disposed on the same plane of the lower substrate, the transmittance and aperture ratio are low. In addition, the IPS LCD device has disadvantages of a relatively slow response time and a relatively small alignment margin. Because of the small alignment margin, the IPS LCD device needs a uniform cell gap.
The IPS LCD device has the above-mentioned advantages and disadvantages. Users may or may not select an IPS LCD device depending on the intended use.
Now, with reference to FIGS. 5, and 6A to 6D, a fabricating process for a conventional IPS LCD device is provided. FIG. 5 is a plan view illustrating a unit pixel region “P” of a conventional IPS LCD device. As shown, a gate line 50 and a common line 54 are arranged parallel to each other, and a data line 60 is arranged perpendicular to the gate and common lines 50 and 54. Near a cross point of the gate and data lines 50 and 60, a gate electrode 52 and a source electrode 62 are disposed. The gate and source electrodes 52 and 62 integrally communicate with the gate line 50 and the data line 60, respectively. The source electrode 62 overlaps a portion of the gate electrode 52. In addition, a drain electrode 64 is disposed opposite to the source electrode 62 with an interval therebetween.
A plurality of common electrodes 54a are disposed perpendicular to the common line 54 and connected thereto. The plurality of common electrode 54a are spaced apart from each other with an equal interval therebetween. A first connecting line 66 integrally communicates with the drain electrode 64, and a plurality of pixel electrodes 66a are disposed perpendicular to the first connecting line 66. First ends of the pixel electrodes 66a are connected with the first connecting line 66, and the second ends of the pixel electrodes 66a are connected with a second connecting line 68 that is disposed over the common line 54. The plurality of common electrodes 54a and pixel electrodes 66a are spaced apart from each other and arranged in an alternating pattern. Therefore, each common electrode 54a is parallel to an adjacent pixel electrode 66a. 
FIGS. 6A to 6D illustrate a sequence of fabricating processes for an array substrate 1 of the above-mentioned IPS LCD device.
As shown in FIG. 6A, on the array substrate 1, a first metal layer is deposited and patterned to form the gate electrode 52 and the plurality of common electrodes 54a. The first metal layer is selected from a group consisting of chromium (Cr), aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), tantalum (Ta), tungsten (W), antimony (Sb), and alloys thereof.
As shown in FIG. 6B, a gate-insulating layer 70 is formed on the array substrate 1 to cover the gate and common electrodes 52 and 54a, and on the gate-insulating layer 70, an active layer 72 is formed over gate electrode 52. The gate-insulating layer 70 is silicon nitride (SiNx) or silicon oxide (SiO2), while the active layer 72 includes an amorphous silicon layer (not shown) and a doped amorphous silicon layer (not shown).
As shown in FIG. 6C, a second metal layer is deposited and patterned to form the source and drain electrodes 62 and 64 on the active layer 72 and the pixel electrodes 66a on the gate-insulating layer 70. The pixel electrodes 66a are spaced apart from the adjacent common electrode 54a by a desired distance.
As shown in FIG. 6D, a passivation layer 74 is formed to cover the source, drain, and pixel electrodes 62, 64, and 66a. The passivation layer 74 serves to protect the source, drain, and pixel electrodes 62, 64, and 66a from exterior humidity or contaminants.
As described above, the plurality of common electrodes 54a of the IPS LCD device are connected with the common line 54. Though the IPS LCD device has an advantage of wide viewing angle because of the above-mentioned structure including the common line 54, the common line 54 of the IPS LCD device is much higher in resistance than the common electrode of the TN LCD device.
That is to say, the common electrode 14 of the TN LCD device in FIG. 1 is uniformly disposed on the overall surface of the upper substrate opposing the pixel electrode. Therefore, the common electrode 14 of the TN LCD device has the shape of a surface and has a relatively low resistance. In contrast, the common line 54 of the IPS LCD device in FIG. 4 has the shape of a line and has a relatively high resistance.
A common voltage signal is applied to the common line 54 of the IPS LCD device or the common electrode 14 of the TN LCD device. In case of the IPS LCD device, because the common line has a relatively high resistance, it is associated with a relatively high voltage drop. Because the common voltage signal is applied from both ends of the common line, the voltage drop is highest at the center of the IPS LCD panel. That is to say, the common voltage signal is decreasing as it transmits from the sides of the IPS LCD panel to the center thereof.
Even if the common voltage signal is adjusted or compensated at an exterior drive circuit, the above-mentioned voltage drop cannot be avoided. The voltage variation due to the voltage drop of the common voltage signal causes fatal defects, for example, a flicker to display quality of the conventional IPS LCD device.
Together with the above-mentioned voltage variation of the common voltage signal, a conventional structure of an inverted-staggered type TFT itself is associated with the flicker problem. The inverted-staggered type TFT is widely selected as a switching element for the LCD devices including the IPS LCD device. The inverted-staggered type TFT has a simple structure to be easily fabricated but exhibits superior electrical qualities. To achieve such superior electrical qualities, a source electrode and a drain electrode of the inverted-staggered type TFT overlap a gate electrode thereof. Specifically, the overlapping width of the drain electrode over the gate electrode is associated with the flicker problem. A detailed explanation will be provided with reference to FIGS. 7 and 8.
In FIG. 7, a first pixel region “A” and a third pixel region “C” are arranged at a left side and at a right side, respectively, with a second pixel region “B” disposed therebetween. In the first to third pixel regions “A” to “C”, drain electrodes 64a to 64c overlap gate electrodes 52a to 52c, respectively. At this point, a first overlapping width “LA”, a second overlapping width “LB”, and a third overlapping width “LC” conventionally have the same value (LA=LB=LC). Within the first to third overlapping widths “LA” to “LC”, a parasitic capacitance “Cgs” exists between the drain electrode 64a (64b, 64c) and the gate electrode 52a (52b, 52c).
In FIG. 8, when a gate voltage signal “Vg” is applied to the TFT (“S” in FIG. 5), the TFT switches a drain voltage signal “Vd” such that a pixel voltage signal “Vp” is applied to the pixel electrode. At this point, a kickback voltage “ΔVp” is induced by the parasitic capacitance “Cgs”, thereby decreasing the pixel voltage signal “Vp” by the kickback voltage “ΔVp”.
The above-mentioned kickback voltage “ΔVp” is conventionally compensated for by adjusting the common voltage signal. However, in case of the IPS LCD device, because the common line has a high resistance, the common voltage signal varies along the common line. Accordingly, the kickback voltage “ΔVp” cannot be compensated for sufficiently, and, thus, the flicker problem occurs in the IPS LCD device.